This invention relates to a storage apparatus that uses a flash memory.
NAND flash memories sometimes suffer from read disturb, which is data destruction caused by read operation. In a NAND flash memory, field effect transistors (FETs) having floating gates are arranged as memory cells in the manner shown in FIG. 1. Several thousand to several ten thousand memory cells are put side by side in a lateral direction, and there are several to several ten memory cells in a longitudinal direction. The memory cells in the same row or column constitute one group, and groups of memory cells constitute a management unit by which data is erased or otherwise managed. Columns of memory cells aligned in the longitudinal direction are obtained by connecting the FETs in series. Electric charges flow into and out of the floating gates through dielectric breakdown or a tunnel effect of an insulating oxide film surrounding the floating gates, which is caused by applying high voltage to source, drain, and gate electrodes.
To read data out of an FET, 0 V is applied to the gate electrode of the chosen FET from which data is to be read whereas Vcc (power supply voltage) is applied to the gate electrodes of the rest of the FETs. Vcc applied to the gate electrodes of the FETs that are not chosen generates a voltage stress in the insulating oxide film, with the result that threshold voltage of the FETs is changed. While Vcc is relatively low voltage compared to write voltage and erase voltage, the application of Vcc generates a large voltage stress in the insulating oxide film at a time of voltage application when the field intensity in a semiconductor is raised by advanced miniaturization of the memory cells.
The threshold voltage of the memory cell FETs that have not been chosen is changed in this manner. When a memory cell FET of which the threshold voltage has thus been changed is chosen in order to read data out of this FET, there is a possibility that wrong data is read.
A technique of preventing such data error is disclosed in JP 2004-326867 A, for example. According to JP 2004-326867 A, data requested by a host is read and an error correction code is used on the read data to detect and correct an error, or judge a degree of error. Before the degree of error reaches a level where correction is not possible, the relevant page is refreshed.